The disclosed embodiments relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a vertical channel transistor.
As dynamic random access memory (DRAM) devices are becoming highly integrated, a feature size is getting smaller and doping concentration to a substrate is gradually increasing. Such a high integration of the device inevitably leads to a junction leakage, a short channel effect, etc., and thus a typical planar transistor is not suitable for a highly integrated device. Further, a channel length and width are limited and electron mobility decreases due to an increase in channel doping concentration, therefore, it is difficult to ensure channel current sufficiently. To overcome the limitation of the typical planar transistor, a vertical channel transistor has been proposed.
FIG. 1 illustrates a cross-sectional view of a typical vertical channel transistor.
Referring to FIG. 1, the typical vertical channel transistor includes a pillar having a body pillar 12 and a head pillar 13 which are obtained by etching a silicon substrate 11, a gate dielectric layer 14 formed over a surface of the body pillar 12, and a surround type gate electrode 15 formed over the gate dielectric layer 14 and surrounding an outer wall of the body pillar 12. A hard mask layer 16 is formed over the head pillar 13, and a capping layer 17 is formed on sidewalls of the head pillar 13 and the hard mask layer 16.
In the typical vertical channel transistor of FIG. 1, the body pillar 12 surrounded by the gate electrode 15 serves as a channel so that the channel is vertically formed. However, in the fabrication of the typical vertical channel transistor, there is difficulty in forming patterns, particularly forming a channel which is most important in a transistor. It is also estimated that there is difficulty in performing a lateral etch for forming a pillar to be used as a vertical channel transistor.
The body pillar 12 is typically formed by a lateral etching such as an isotropic dry etching. Hence, a width of the body pillar 12 may not be easily adjusted, leading to the formation of a pillar with a non-uniform linewidth. Further, if the width of the body pillar 12 is small, the pillar may collapse. Since the pillar is formed through etching process in the typical vertical channel transistor, it is difficult to perform a pillar forming process, thus reducing reliability of the vertical channel transistor.